1. Technical Field
This invention relates generally to semiconductor devices, and more particularly, to the programming of an electrically programmable and erasable memory cell.
2. Background Art
A type of programmable memory cell is commonly referred to as a flash memory cell. Such flash memory cell may include a source and a drain formed in a silicon substrate, or in a well that is formed in the silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of the flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as a tunnel oxide layer. A memory cell of this type is shown and described in U.S. Pat. No. 4,698,787, xe2x80x9cSingle Transistor Electrically Programmable Memory Device and Methodxe2x80x9d, issued to Mukherjee et al. on Oct. 6, 1987.
Programming operations on a flash memory cell involve the application of a relatively large constant voltage to the drain of the flash memory cell while an even larger voltage is applied to the control gate. During such a programming operation, the source of the flash memory cell is maintained at a ground level or a zero voltage level in relation to the voltages applied to the control gate and drain. The high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation. Such a high voltage potential on the floating gate attracts the electrons floating through the channel region. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is commonly referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve a desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of the flash memory cell to cause conduction through the channel region during the read operation on the flash memory cell.
In a typical memory array which includes a large number of cells, a cell can be programmed by applying programming voltages of approximately 9-10 volts to the control gate, approximately 5 volts to the drain, and grounding the source. These voltages cause hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold of the cell to a value in excess of approximately 4 volts.
A cell can be read by applying a voltage of approximately 5 volts to the control gate, applying approximately 1 volt to the bit line to which the drain is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltage is relatively high (5 volts), the bit line current will be zero or relatively low. If the cell is not programmed or is erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bit line current will be relatively high.
A cell can be erased in several ways In one approach, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Applying a negative voltage on the order of xe2x88x9210 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase the cell. Another method of erasing a cell is by applying 5 volts to the P well and xe2x88x9210 volts to the control gate while allowing the source and drain to float.
A memory cell 20 of this type is shown in FIG. 1. The cell 20 is one cell in an array thereof and includes a single transistor 22 having a source 24 and a drain 26 formed in a silicon substrate 28, and a gate stack 30 formed on the silicon substrate 28. The gate stack 30 of the flash memory cell 28 has a tunnel oxide 32 on the substrate 28 over the channel region between the source 24 and the drain 26, a polysilicon floating gate 34 on the tunnel oxide 32, a dielectric, for example ONO layer 36 on the floating gate 34, and a polysilicon control gate 38 of the dielectric layer 36.
During programming of the memory cell 20, chosen voltages are applied to the source 24 and drain 26 (for example grounding the source 24 and applying 5 volts to drain 26), and voltage Veg, applied to the control gate 38 is ramped up from zero, increasing in a linear manner in direct proportion to time as shown in FIG. 3. This increasing voltage applied to the control gate 38 causes the threshold voltage Vt of the cell 20 to increase with time (utilizing hot carrier injection) in accordance with for example the curve B shown in FIG. 4, which is an example of a plot of threshold voltage Vt of a cell against log time. As noted, the programmed threshold voltage Vt increases with time, being of moderate initial steepness, with the steepness thereof gradually decreasing as the voltage applied to the control gate 38 continues to be ramped up.
Starting with and during ramping up of the voltage to the control gate 38, at a succession of times separated by substantially equal time intervals, a corresponding succession of verification tests are undertaken, to determine the threshold voltage of the cell 20 at any given test time and to verify if the cell 20 has been programmed to a chosen threshold level Vt1. When a verification test has revealed for the first time that the threshold voltage of the cell 20 has reached the chosen threshold voltage Vt1, ramping up of voltage on the control gate 38 continues, and another, successive verification test is undertaken at the next successive time to again verify that the threshold voltage of the cell 20 has indeed reached the chosen threshold voltage Vt1. If it is again determined that the threshold voltage of the cell 20 has reached the chosen threshold voltage Vt1, voltage to the control gate 38 discontinued and the cell 20 is considered programmed.
The practice of this process in accordance with the above description can lead to substantial variations in the threshold voltages of programmed cells. Because of variations in the manufacturing process of the cells, the rate of programming times will vary slightly from cell to cell. This is illustrated by the three examples of threshold programming curves A, B, C of FIG. 4, corresponding to the programming of three different cells. If for each cell the successive verification tests are undertaken at the same times after initiation of the programming process, the programmed threshold levels for these cells can vary by differing levels from the chosen Vt1, as will now be described.
FIGS. 5, 6 and 7 show portions of the threshold programming curves A, B, and C respectively. In FIG. 5, for a cell having a threshold programming curve for example shown at curve A, FIG. 4, at time t1 after initiation of the programming process, a verification test (one of a successive series thereof as described above) is undertaken, immediately prior to the cell being programed to the chosen threshold voltage Vt1, i.e., that time of the last verification test that has indicated that the threshold voltage Vt1 has not yet been reached. Then, at the next successive time t2 of the next successive verification test, another verification test is undertaken, verifying that for the first time that the threshold voltage of the cell has reached the chosen threshold voltage Vt1. Then, in accordance with the above described process, at the next successive time t3 (t2xe2x88x92t1=t3xe2x88x92t2) of the next successive verification test, another verification test is undertaken to again verify that the threshold voltage of the cell has reached the chosen threshold voltage Vt1. In this cell, the verification test undertaken at time t2 has verified the threshold voltage of the cell as very close to the chosen threshold voltage Vt1 (FIG. 5), and the next successive verification test at time t3 verifies an actual threshold voltage of the cell further above the chosen threshold voltage Vt1.
Referring to FIG. 6, for a different cell having a slightly different threshold programming curve (for example curve B in FIG. 4), again at time t1 after initiation of the programming process (the interval from the initiation of the programming process to time t1 being the same in both examples), a verification test (one of a successive series thereof as described above) is undertaken, immediately prior to the cell being programmed to the chosen threshold voltage Vt1, i.e., that time of the last verification test that has indicated that the threshold voltage Vt1 has not yet been reached. Then, at the next successive time t2 (interval between t1 and t2 being the same as in the previous example), another verification test is undertaken, verifying that the threshold voltage of the cell has for the fist time reached the chosen threshold voltage Vt1. For this cell, the verification test taken at time t2 has verified the threshold voltage of the cell as not as close to the chosen threshold voltage Vt1 as in the previous example, due to variations in the threshold programming curve from cell to cell as described above. The next successive verification test at time t3 (interval between t2 and t3 the same as in the previous example) will verify an actual threshold voltage of the cell further above the chosen threshold voltage Vt1 than in the previous example, as will be seen when comparing FIG. 5 and FIG. 6.
Referring to FIG. 7, for yet another different cell having a slightly different threshold programming curve (for example curve C in FIG. 4), again at time t1 after initiation of the programming process (the interval from the initiation of the programming process to time t1 being the same in all three examples), a verification test (one of a successive series thereof as described above) is undertaken, immediately prior to the cell being programmed to the chosen threshold voltage Vt1, i.e., that time of the last verification test that has indicated that the threshold voltage Vt1 has not yet been reached. Then, at the next successive time t2 (interval between t1 and t2 being the same as in the previous examples), another verification test is undertaken, verifying that the threshold voltage of the cell has for the first time reached the chosen threshold voltage Vt1. For this cell, the verification test taken at time t2 has verified the threshold voltage of the cell as not as close to the chosen threshold voltage Vt1 as in the previous example, due to variations in the threshold programming curve from cell to cell as described above. The next successive verification test at time t3 (interval between t2 and t3 the same as in the previous examples) will verify an actual threshold voltage of the cell further above the chosen threshold voltage Vt1 than in the previous example, as will be seen when comparing FIG. 6 and FIG. 7.
As will be seen, the difference between the actual threshold voltage of a cell and its targeted threshold voltage Vt1 varies significantly from cell to cell (compare the threshold programming curves A, B and C of FIGS. 4, 5, 6 and 7 and the differences X, Y and Z between the actual threshold voltage of a cell and its targeted threshold voltage Vt1, FIGS. 5, 6 and 7 for the three examples given). This is due to the fact that the steepness of the threshold programming curves decrease only gradually upon increase in voltage applied to the control gate, so that the slope of the curve in the region of Vt1 is still significant, causing a relatively large increase in cell threshold voltage for a giving time difference between successive verifications of threshold voltage. This results in programmed cells in an array having a wide variation in threshold voltage.
FIG. 2 is a graph illustrating threshold voltage distribution vs. number of cells (curve DIST1) in a flash memory array wherein the cells are programmed by the above method, indicating the significant variation in threshold voltage of the cells. This wide variation can lead to serious operational difficulties in the array, slowing down operation of the array.
In addition, with the steepness or slope of a programmed threshold voltage curve being only moderate as the voltage applied to the control gate is ramped up (FIG. 4), a substantial amount of time is required to reach the targeted threshold voltage Vt1, slowing down operation of the array.
Therefore, what is needed is a method for tightening the voltage threshold distribution of the cells of a memory array an increasing the programming speed thereof.
The present method is for programing the threshold voltage of a memory cell transistor having a substrate, a gate insulator on the substrate, a floating gate on the gate insulator, an insulating layer on the floating gate, and a control gate on the insulating layer, and a source and drain in the substrate. In the present method, a voltage difference is applied between the drain and source of the transistor. A negative voltage is applied to the substrate of the transistor. An increasing voltage is applied to the control gate of the transistor, and, during application of that increasing voltage to the control gate of the transistor, a succession of verification tests are undertaken at a corresponding succession of times separated by chosen time intervals to verify if the transistor has been programmed to a chosen threshold voltage.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.